Career
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Digital Design & Verification Engineer
June 2022 – Present
Contributed to IP verification projects (e.g., CAN, 1G Ethernet, DMA IPs), SoC verification projects (SoCs utilizing RISC-V and Arm cores), avionics projects (including DO-254 and AMC 20-152A compliance), and internal tooling development.
Key Technologies & Methodologies:
- SystemVerilog UVM and SystemVerilog Assertions (SVA)
- Metric-Driven Verification (MDV)
- Tools: Cadence Xcelium, Verisium Debug, Verisium Manager, Synopsys VCS
- VIPs: Cadence, Synopsys, Truechip
- RISC-V Instruction Set Architecture (ISA) and Spike Instruction Set Simulator
- Bare-metal programming with C
- Design Assurance Guidance for Airborne Electronic Hardware (DO-254) and Development Assurance for Airborne Electronic Hardware (AMC 20-152A)
- Python-based verification utilities and internal tooling development
- Version Control: Git, GitLab CI, SVN -
Non-Matriculated Researcher
November 2023 - April 2024
Advanced Computer Architecture Lab. @Yeditepe University
Following my master's graduation, upon mutual agreement with my advisor, I am continuing to study in the field of computer architecture as a member of the Advanced Computer Architecture Lab. Currently, I am focusing on machine learning on hardware and implementing the proposed designs not only on simulators but on hardware itself.
Advisor: Prof. Gürhan Küçük -
Graduate Student Researcher
June 2022 - October 2023
Advanced Computer Architecture Lab. @Yeditepe University
Took part in several projects and studies regarding achieving energy-efficient, secure, and quality-of-service-satisfying core microarchitectures on SMT processors using gem5 and SimpleScalar variant M-Sim system simulators.
Advisor: Prof. Gürhan Küçük -
Teaching Assistant
September 2021 - June 2022
Lectured lab hours for the courses
- CSE 114 - Fundamentals of Computer Programming (C)
- CSE 211 - Data Structures (C++)
- CSE 221 - Principles of Logic Design
- CSE 232 - Systems Programming (Assembly Language)
- CSE 331 - Operating Systems Design (C)
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Academic and Scientific Editor
September 2021 - June 2022
Fixed grammar errors, ambiguities, journal guideline incompatibilities, and improved overall readability alongside with scientific cross-cheking of academic papers (in fields of computer and electronics engineering) pre-publishing. -
Undergraduate Researcher
September 2018 - February 2020
Advanced Computer Architecture Lab. @Yeditepe University
Worked on power-efficient core architectures using gem5 and SimpleScalar variant M-Sim system simulators.
Advisor: Prof. Gürhan Küçük -
Software Engineer Intern
September 2018 - February 2020
Worked as a member of Software Design Team on improving service interfaces in surveillance systems. -
Undergraduate Researcher
June 2017 - August 2017
VR and Robotics Lab. @Yeditepe University
Summer study on production line automation using ROS and Copella Robotics' V-REP.
Advisor: Assist. Prof. Ayşe Küçükyılmaz
Publications
As per the meme quotes: Well, it's not much, but it's honest work.
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Breaking the complexity barrier: Enhancing quality of service in simultaneous multithreading processors
Available at SSRN 5109491, 2025
Within the wide variety of applications running in the cloud, demands for service quality and performance guarantees need special attention. Since cloud nodes typically utilize Simultaneous Multithreading (SMT) cores, processor resources may need to be shared and managed among multiple applications. A customer application that demands high levels of Quality of Service (QoS) may require more resources than its best-effort allocated share. QoSMT is an earlier study that focuses on 2-thread SMT cores to address this issue. While a simple relationship between two threads may be relatively straightforward to manage, the interactions among multiple threads can quickly become highly complex and difficult to design and maintain. In this paper, we extend the original QoSMT study to 4-thread SMT cores by proposing three alternative scheduling algorithms that regulate resource usage between a high-priority thread and three ordinary batch-type threads. On average, we achieve 7.2% better overall throughput and up to 218% better throughput for the latency-sensitive, high-priority thread. More than 92% of 600 workloads display higher performance than the baseline configuration, and 8% of workloads perform ten times better compared to a traditional 4-thread baseline SMT with unmanaged resources.
Citation: Sari, Sercan & Nezir, Ugur & Demir, Onur & Kucuk, Gurhan. (2025). Breaking the Complexity Barrier: Enhancing Quality of Service in Simultaneous Multithreading Processors. 10.2139/ssrn.5109491.
Download Paper | No Slides Available -
Optimizing QoS and Throughput on 4-Thread SMT Processors
MSc. Thesis - Yeditepe University Graduate School of Natural & Applied Sciences, 2023
Simultaneous multithreading (SMT) is one of the key performance features in modern processors. However, in data center applications where immense computing power is required, there is a certain aspect that is much more important than overall performance: Quality of service. SMT, though, meanwhile getting its strength from sharing resources between multiple threads in a core, actually hurts the throughput of singular workloads, and a significant amount of these workloads require an exorbitant degree of quality of service. Thus, SMT, which is one of the breakthroughs lying under the modern processor microarchitecture, actually hurts data center applications due to its sharing nature. This handicap even leads the data centers to the point of disabling SMT on their processors to preserve their required quality of service. This topic has been occasionally studied in the literature and several propositions were made to overcome this barrier and obtain higher performance and increase performance per Watt and performance per total cost of ownership dollars. One of the leading studies is QoSMT which aims to enable a quality of service satisfying SMT approach in data centers. It achieves so by implementing a statistic-based dynamic resource partitioning scheme. However, the original QoSMT paper implements a design for two-threaded SMT cores meanwhile the modern data center processors use four or eight threads. When there are only two threads in a core, there is only a single transaction pathway between threads. High priority thread (HPT) takes or gives resources from/to low priority thread. When the thread count increases though, a necessity for resource scheduling arises as well and the statistical accuracy of partition decisions naturally degrades. In this study, we take the baseline QoSMT study, implement it, extend it to four-threaded SMT cores, suggest and implement some overall design improvements and analyze its capabilities for three different scheduling algorithms. We observe that our proposed best designs provided up to 66.63% quality of service improvements compared to the baseline SMT with only a 7.09% loss of total performance in terms of IPC.
Citation: Nezir, Ugur. (2023). Optimizing QoS and Throughput on 4-Thread SMT Processors. 10.13140/RG.2.2.11506.62401.
Download Paper | No Slides Available -
GQoSMT: On Guaranteeing the Quality of Service Requirements of Simultaneous Multithreading Processors
2023 8th International Conference on Computer Science and Engineering (UBMK), 2023
Guaranteeing the quality of service of a running thread on a Simultaneous Multithreading processor is one of the most challenging issues since these processors allow sharing of many datapath resources, including the Issue Queue, the Reorder Buffer, the Load/Store Queue, the branch prediction circuit, and multiple levels of the caches among multiple threads. In this study, we apply machine learning techniques to accurately predict the instant quality of service of a target thread so that we can transfer just a sufficient amount of shared resources to keep its quality of service stable at an expected level. Our test results show that our proposed prediction model gives only around 3% deviation from the target quality of service level, on average, whereas an earlier prediction model gives more than a 13% deviation.
Citation: Kucuk, Gurhan & Tokatli, Nazli & Nezir, Ugur & Pektaş, Elif & Mete, Emrah & Gökhan Gökçek, Gülşah & Yıldız Güney, Merve & Alsharif, Salwa & Baiat, Zahra. (2023). GQoSMT: On Guaranteeing the Quality of Service Requirements of Simultaneous Multithreading Processors. 234-239. 10.1109/UBMK59864.2023.10286669.
Download Paper | No Slides Available -
A Simulated Case Study of Smart Grid's Impact on Enabling Renewable Energy
2022 International Conference on Smart Applications, Communications and Networking (SmartNets), 2022
Renewable energy is a hot-topic for many researchers and companies alike because of the environmental concerns about current means of energy production. However, many kinds of renewable energy sources generate fluctuating power, which is hard to load-balance through different days of a month, or even hours of a day. This consistency problem increases the need for energy storage improvement. In this study, we elaborate on if an IoT enabled smart-grid application can successfully manage energy consistency for households through using electric vehicles as mobile storage means. We designed and implemented a highly-realistic projection for a city of Turkey, Denizli to observe the impact of using electric vehicles within a solar powered grid. The simulation results reveal that the proposed solution provides self-sufficient uptimes more than twice of the standalone grid with uptimes up to 100%, showcasing an immense potential for such applications.
Citation: Nezir, Ugur & Bali, İbrahim & Baydere, Sebnem. (2022). A Simulated Case Study of Smart Grid's Impact on Enabling Renewable Energy. 1-6. 10.1109/SmartNets55823.2022.9993986.
No Downloads Available | No Slides Available -
Improved Resource Scheduling for Lightweight SMT-COP
2021 6th International Conference on Computer Science and Engineering (UBMK), 2021
Simultaneous multithreading (SMT) processors target resource under-utilization related performance problems of superscalar processors by allowing various datapath resources to be simultaneously shared among several threads with ease. This approach exploits thread-level parallelism on top of the well-studied instruction level parallelism. However, when datapath resources are shared among threads, there is always a possibility that corunning ill-intended programs may try to sniff on other programs with sensitive information like passwords or cryptocurrency information. By stress-testing and measuring many of the shared resources, this is quite achievable. These approaches are known as side-channel attacks. SMT-COP, a study published recently, is a secure architectural implementation based on resource scheduling that prevents these kind of attacks based on execution logic with a modest performance loss of nearly 10%. In this study, we aim to improve SMT-COP’s resource distribution scheme with several approaches, providing a quite close sense of security to that of SMT-COP while improving the performance by up to 8.86% on the average, over the original SMT-COP design.
Citation: Nezir, Ugur & Lus, Burak & Kucuk, Gurhan. (2021). Improved Resource Scheduling for Lightweight SMT-COP. 575-580. 10.1109/UBMK52708.2021.9558934.
Download Paper | No Slides Available -
ShapeShifter: A Morphable Microprocessor for Low Power
Turkish Journal of Electrical Engineering and Computer Sciences, 2021
A composite core contains large and small heterogeneous microengines. The most important property of composite cores is their ability to select the most proper microengine for running applications to save power without sacrificing too much performance. To achieve this, a composite core tries to predict the performance of the passive microengine by collecting various processor statistics from the active microengine at runtime. In the method proposed in the literature, the microengine, which is more ideal for running the rest of the application, is determined by a migrationdecision circuitry that is bound to collected statistics and complex functions, which are run in a sequential manner. In this study, we propose the ShapeShifter architecture that holds a single out-of-order core to switch its mode of instruction execution between out-of-order and in-order modes. With a simple mode-change decision circuitry, which is bound to only two processor statistics, we can save more than 25% power, more than 21% on energy-delay product, and more than 16% on energy-delay-square product on the average, by only sacrificing less than 5% of performance.
Citation: Tokatli, Nazli & Guney, Isa & Sari, Sercan & Yıldız Güney, Merve & Nezir, Ugur & Kucuk, Gurhan. (2021). ShapeShifter: A Morphable Microprocessor for Low Power. Turkish Journal of Electrical Engineering and Computer Sciences. 29. 10.3906/elk-2005-180.
Download Paper | No Slides Available
Teaching
Document your teaching roles, workshops, or mentoring experiences here.
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Course or Workshop #1
Spring 2023
Short description of your role and the course/workshop content ...
Non-Professional Interests
Well, this is just an irrelevant section. (:
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Role-Playing Games
Started in 2015
I have been playing and running tabletop RPGs for a very long while.
My favorite setup is medieval fantasy, and I mostly run Pathfinder 2e games when I am the gamemaster. I mostly prefer to play with my friends; however, I occasionally GM for events and conventions.
I have GM'd or played games of varying systems and themes:
- Pathfinder 1e & 2e (Medieval Fantasy)
- Vampire the Masquerade v20 (Modern Dark Fantasy)
- Legend of the Five Rings (Asian Fantasy)
- Dungeons & Dragons 3.5 and 5e (Medieval Fantasy)
- Deadlands (Western Horror)
- Custom Harry Potter systems (Urban Fantasy)
- Star Wars RPG (Science Fiction Fantasy)
- GURPS 4th Edition (Science Fiction Fantasy)
- Call of Cthulhu 7th Edition (Modern Dark Horror)
- 7th Sea 2nd Edition (Swashbuckling)
- Alien RPG (Science Fiction Fantasy)
I also enjoy text-based PBP roleplaying games since 2020.
- I have played in several Turkish and English websites, mostly on Harry Potter-based plots.
- I have created my own Harry Potter RPG website, plot, and system with a group of friends and ran it for two years. More than a hundred players joined and more than four hundred characters were created.
- I have designed systems, coded Discord bots, and advised storylines for some other PBP Discord RPG servers later as a hobby.
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Board Games
Started in 2015
Board games have been my introduction into the geek subculture.
I mostly enjoy engine-building, euro, and deck-building games with enjoyable themes. For seven years, I have worked as a volunteer board-game staff for conventions with varying sizes of 100-1,500 attendees, introducing and teaching board games to both veterans and newcomers.
Board games that I have played so far:
- Root
- Spirit Island
- Horizons of Spirit Island
- Terraforming Mars
- Gloomhaven
- Clank!: Catacombs
- Clank!
- Wingspan
- Nemesis
- Lost Ruins of Arnak
- Hegemony: Lead Your Class to Victory
- Scythe
- Blood Rage
- Lords of Waterdeep
- XCOM: The Board Game
- 7 Wonders Duel
- A Game of Thrones: Board Game
- Twilight Struggle
- Dune: Imperium
- Between Two Cities
- Detective: A Modern Crime
- Settlers of Catan
- Settlers of Catan: Cities & Knights
- Star Wars: Imperial Assault
- Skyteam
- Beast
- Targi
- Splendor
- Splendor Duel
- Champions of Midgard
- Tsuro
- Azul
- Dead of Winter
- World of Warcraft
- Dungeons & Dragons
- Marvel Champions
- Ticket to Ride
- Codenames
- Carcassonne
- Secret Hitler
- Resistance
- Cascadia
- The Crew
- Coup
- Munchkin
- Citadels